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2-mbit (128k x 16) static ram cy62137v mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05051 rev. *e revised july 19, 2006 features ? high speed ?55 ns ? temperature ranges ? industrial: ?40c to 85c ? automotive: ?40c to 125c ? wide voltage range: 2.7v ? 3.6v ? ultra-low active, standby power ? easy memory expansion with ce and oe features ? ttl-compatible inputs and outputs ? automatic power-down when deselected ? cmos for optimum speed/power ? available in pb-free and non pb-free standard 44-pin tsop type ii package functional description [1] the cy62137v is a high-performance cmos static ram organized as 128k words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that reduces power consumption by 99% when addr esses are not toggling. the device can also be put into standby mode when deselected (ce high) or when ce is low and both ble and bhe are high. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. logic block diagram 128k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we ble bhe a 16 a 0 a 1 a 9 power - down circuit ble a 10 10 note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com ce bhe [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 2 of 11 product portfolio product v cc range (v) speed (ns) grades power dissipation operating, i cc (ma) standby, i sb2 ( a) min. typ. [2] max. typ. [2] max. typ. [2] max. cy62137vll 2.7 3.0 3.6 55 industrial 7 20 1 15 70 7 15 1 15 70 automotive 7 15 1 20 pin configurations [3] we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii (forward) 12 13 41 44 43 42 16 15 29 30 v cc a 16 a 15 a 14 a 13 a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 nc v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 a 12 pin definitions pin number type description 1?5, 18?22, 24?27, 42?45 input a 0 ?a 16 . address inputs 7?10, 13?16, 29?32, 35?38 input/output i/o 0 ?i/o 15 . data lines. used as input or output lines depending on operation 23 no connect nc . this pin is not connected to the die 17 input/control we . when selected low, a write is co nducted. when selected high, a read is conducted 6 input/control ce . when low, selects the chip. when high , deselects the chip 40, 39 input/control bhe , ble . bhe = low selects higher order byte writes or reads on the sram ble = low selects lower order byte writes or reads on the sram 41 input/control oe . output enable. controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high , i/o pins are tri-stated, and act as input data pins 12, 34 ground v ss . ground for the device 11, 33 power supply v cc . power supply for the device notes: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) ., t a = 25c. 3. nc pins are not connected on the die. [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 3 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [4] ....................................?0.5v to v cc + 0.5v dc input voltage [4] .................................?0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ...... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc industrial ?40c to +85c 2.7v to 3.6v automotive ?40c to +125c 2.7v to 3.6v electrical characteristics over the operating range parameter description test conditions cy62137v-55 cy62137v-70 unit min. typ. [2] max. min. typ. [2] max. v oh output high voltage i oh = ?1.0 ma v cc = 2.7v 2.4 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5v 2.2 v cc + 0.5v v v il input low voltage ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current i out = 0 ma, f = f max = 1/t rc , cmos levels v cc = 3.6v 7 20 7 15 ma i out = 0 ma, f=1mhz, cmos levels 12 12ma i sb1 automatic ce power-down current?cmos inputs ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = f max v cc = 3.6v 100 100 a i sb2 automatic ce power-down current?cmos inputs ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v, f = 0 v cc = 3.6v industrial 1 15 1 15 a automotive 1 20 capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 6pf c out output capacitance 8 pf thermal resistance [5] parameter description test conditions tsopii unit ja thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 2-layer printed circuit board 60 c/w jc thermal resistance (junction to case) 22 c/w notes: 4. v il (min.) = ?2.0v for pulse durations less than 20 ns. 5. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 4 of 11 ac test loads and waveforms parameters 3.0v unit r1 1105 ohms r2 1550 ohms r th 645 ohms v th 1.75 volts data retention characteristics (over the operating range) parameter description conditions min. typ. [2] max. unit v dr v cc for data retention 1.0 v i ccdr data retention current v cc = 1.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, no input may exceed v cc +0.3v industrial 0.5 7.5 a automotive 10 t cdr [5] chip deselect to data retention time 0ns t r operation recovery time 70 ns data retention waveform v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v equivalent to: the venin equivalent all input pulses r th r1 v cc output 5 pf including jig and scope (b) r1 r2 (a) rise time: 1 v/ns fall time: 1 v/ns (c) v cc (min.) v cc (min.) t cdr v dr > 1.0 v data retention mode t r ce v cc [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 5 of 11 switching characteristics over the operating range [6] parameter description 55 ns 70 ns unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low-z [7] 55ns t hzoe oe high to high-z [7, 8] 25 25 ns t lzce ce low to low-z [7] 10 10 ns t hzce ce high to high-z [7, 8] 25 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 55 70 ns t dbe bhe /ble low to data valid 55 70 ns t lzbe [9] bhe /ble low to low-z 5 5 ns t hzbe bhe /ble high to high-z 25 25 ns write cycle [10, 11] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 50 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [7, 8] 20 25 ns t lzwe we high to low-z [7] 510ns t bw bhe /ble low to end of write 50 60 ns notes: 6. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input levels of 0 to v cc typ., and output loading of the specified i ol /i oh and 30 pf load capacitance. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in (b) of ac test loads. transiti on is measured 500 mv from steady-state voltage. 9. if both byte enables are toggled together this value is 10 ns. 10. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 11. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 6 of 11 switching waveforms read cycle no. 1 (address transition controlled) [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance t hzoe t hzce t pd t hzbe t lzoe t do e t lzoe t dbe impedance high i cc i sb data out oe ce v cc supply current bhe /ble address [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 7 of 11 write cycle no. 1 (we controlled) [10, 15, 16] write cycle no. 2 (ce controlled) [10, 15, 16] notes: 15. data i/o is high-impedance if oe = v ih 16. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 17. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid note 17 t bw data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc data in valid note 17 t bw t sa t hzoe ce address we data i/o oe bhe /ble [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 8 of 11 write cycle no. 3 (we controlled, oe low) [11, 16] write cycle no. 4 (bhe /ble controlled, oe low) [17] switching waveforms (continued) t hd sd t ha data in valid t lzwe t sa t aw t hzwe note 17 t bw t wc ce address we data i/o bhe /ble t t hd t sd t lzwe t sa t ha t aw t wc t hzwe data in valid t bw note 17 ce address we data i/o bhe /ble [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 9 of 11 typical dc and ac characteristics 30 35 25 15 10 5 1.0 1.9 2.8 3.7 0 20 i sb ( a) 1.2 1.4 1.0 0.6 0.4 0.2 1.7 2.2 2.7 3.2 3.7 0.0 0.8 i cc 70 80 60 40 30 20 1.0 1.9 2.8 3.7 supply voltage (v) access time vs. supply voltage 10 50 t aa (ns) normalized operating current standby current vs. supply voltage supply voltage (v) supply voltage (v) mobl mobl mobl vs. supply voltage 2.7 2.7 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high-z deselect/power-down standby (i sb ) l x x h h high-z deselect/power-down standby (i sb ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) lhlhlhigh-z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); high-z (i/o 0 ?i/o 7 ) read active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l high-z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); high-z (i/o 0 ?i/o 7 ) write active (i cc ) l h h l l high-z deselect/output disabled active (i cc ) l h h h l high-z deselect/output disabled active (i cc ) l h h l h high-z deselect/output disabled active (i cc ) [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 10 of 11 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and more battery life is a tra demark, of cypress semiconducto r corporation. all product and company names mentioned in this document are the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 55 cy62137vll-55zi 51-85087 44-pin tsop ii industrial cy62137vll-55zxi 44-pin tsop ii (pb-free) 70 cy62137vll-70zi 44-pin tsop ii cy62137vll-70zxi 44-pin tsop ii (pb-free) cy62137vll-70ze 44-pin tsop ii automotive cy62137vll-70zxe 44-pin tsop ii (pb-free) CY62137VLL-70ZSXE 44-pin tsop ii (pb-free) please contact your local cypress sales representative for availability of these parts package diagrams max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy62137v mobl ? document #: 38-05051 rev. *e page 11 of 11 document history page document title: cy62137v mobl ? 2m (128k x 16) static ram document number: 38-05051 rev. ecn no. issue date orig. of change description of change ** 109960 10/03/01 szv changed from spec number: 38-00738 to 38-05051 *a 116788 09/04/02 gbi added footnote number one added sl power bin deleted fbga package; replacement fb ga package is available in cy62137cv30 *b 237428 see ecn aju added automotive product information *c 329640 see ecn aju changed tsopii package name from z44 to zs44 added pb-free ordering information *d 372074 see ecn syt added pb-free ordering information for automotive *e 486789 see ecn vkn changed address of cypress semi conductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed sl power bin updated ordering information table [+] feedback [+] feedback

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